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1 single, low voltage digitally controlled potentiometer (xdcp?) isl23415 the isl23415 is a volatile, low voltage, low noise, low power, spi? bus, 256 taps, single digitally controlled potentiometer (dcp), which integrates dcp co re, wiper switches and control logic on a monolithic cmos integrated circuit. the digitally controlled potent iometer is implemented with a combination of resistor elements and cmos switches. the position of the wipers are cont rolled by the user through the spi bus interface. the potentiometer has an associated volatile wiper register (wr) that can be directly written to and read by the user. the contents of the wr controls the position of the wiper. when powered on, the isl23415?s wiper will always commence at mid- scale (128 tap position). the low voltage, low power consumption, and small package of the isl23415 make it an ideal choice for use in battery operated equipment. in addition, the isl23415 has a v logic pin allowing down to 1.2v bus operation, independent from the v cc value. this allows for low logic levels to be connected directly to the isl23415 without passing through a voltage level shifter. the dcp can be used as a three- terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. features ? 256 resistor taps ? spi serial interface - no additional level translator for low bus supply - daisy chaining of multiple dcp ?power supply -v cc = 1.7v to 5.5v analog power supply -v logic = 1.2v to 5.5v spi bus/logic power supply ? wiper resistance: 70 typical @ v cc = 3.3v ? shutdown mode - forces the dcp into an end-to-end open circuit and rw is shorted to rl internally ? power-on preset to mid-scale (128 tap position) ? shutdown and standby current <2.8a max ? dcp terminal voltage from 0v to v cc ?10k , 50k or 100k total resistance ? extended industrial temperat ure range: -40c to +125c ? 10 ld msop or 10 ld tqfn packages ? pb-free (rohs compliant) applications ? power supply margining ? rf power amplifier bias compensation ?lcd bias compensation ? gain adjustment in battery powered instruments ? portable medical equipment calibration figure 1. forward and back ward resistance vs tap position, 10k figure 2. v ref adjustment 0 2000 4000 6000 8000 10000 0 50 100 150 200 250 tap position (decimal) resistance ( ? ) august 16, 2011 fn7780.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2010, 2011. all rights reserved intersil (and design) and xdcp are trademarks owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl23415 2 fn7780.1 august 16, 2011 block diagram level shifter v cc rh gnd rl rw sck sdi sdo cs power-up interface, control and status logic wr volatile register and wiper control circuitry v logic i/o block pin configurations isl23415 (10 ld msop) top view isl23415 (10 ld tqfn) top view 1 2 3 4 5 6 10 9 8 7 sdo v logic cs sdi gnd sck rl rw rh v cc o 9 8 7 6 1 2 3 4 rl cs v cc rh gnd sck sdi 5 10 sdo o rw v logic pin descriptions msop tqfn symbol description 110v logic spi bus/logic supply. range 1.2v to 5.5v 2 1 sck logic pin - serial bus clock input 3 2 sdo logic pin - serial bus data output (configurable) 4 3 sdi logic pin - serial bus data input 5 4 cs logic pin - active low chip select 65 rldcp ?low? terminal 76 rwdcp wiper terminal 8 7 rh dcp ?high? terminal 98 v cc analog power supply. range 1.7v to 5.5v 10 9 gnd ground pin
isl23415 3 fn7780.1 august 16, 2011 ordering information part number (note 5) part marking resistance option (k ? ) temp. range (c) package (pb-free) pkg. dwg. # isl23415tfuz (notes 1, 3) 3415t 100 -40 to +125 10 ld msop m10.118 isl23415ufuz (notes 1, 3) 3415u 50 -40 to +125 10 ld msop m10.118 isl23415wfuz (notes 1, 3) 3415w 10 -40 to +125 10 ld msop m10.118 isl23415tfruz-t7a (notes 2, 4) he 100 -40 to +125 10 ld tqfn 2.1x1.6 l10.2.1x1.6a isl23415tfruz-tk (notes 2, 4) he 100 -40 to +125 10 ld tqfn 2.1x1.6 l10.2.1x1.6a isl23415ufruz-t7a (notes 2, 4) hd 50 -40 to +125 10 ld tqfn 2.1x1.6 l10.2.1x1.6a isl23415ufruz-tk (notes 2, 4) hd 50 -40 to +125 10 ld tqfn 2.1x1.6 l10.2.1x1.6a isl23415wfruz-t7a (notes 2, 4) hc 10 -40 to +125 10 ld tqfn 2.1x1.6 l10.2.1x1.6a isl23415wfruz-tk (notes 2, 4) hc 10 -40 to +125 10 ld tqfn 2.1x1.6 l10.2.1x1.6a notes: 1. add ?-tk? or ?-t7a? suffix for tape and reel option . please refer to tb347 for details on reel specifications. 2. please refer to tb347 for details on reel specifications. 3. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 4. these intersil pb-free plastic packaged products employ specia l pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 termination finish, which is rohs compliant and compatible with both snpb an d pb-free soldering operations. intersil p b-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 5. for moisture sensitivity level (msl), please see device information page for isl23415 . for more information on msl please see techbrief tb363 .
isl23415 4 fn7780.1 august 16, 2011 absolute maximum rating s thermal information supply voltage range v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v v logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v voltage on any dcp terminal pin . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v voltage on any digital pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v wiper current i w (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . .6.5kv cdm model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . . . . . . . . 1kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . . 200v latch up (tested per jesd-78b; class 2, level a) . . . . . . . . . . 100ma @ +125c thermal resistance (typical) ja (c/w) jc (c/w) 10 ld msop package (note 6, 7). . . . . . . . 170 70 10 ld tqfn package (note 6, 7) . . . . . . . 145 90 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c v cc supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7v to 5.5v v logic supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2v to 5.5v dcp terminal voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to v cc max wiper current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3ma caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 7. for jc , the ?case temp? location is the center top of the package. analog specifications v cc = 2.7v to 5.5v, v logic = 1.2v to 5.5v over recommended operating conditions unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +125c. symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units r total r h to r l resistance w option 10 k ? u option 50 k ? t option 100 k ? r h to r l resistance tolerance -20 2 +20 % end-to-end temperature coefficient w option 175 ppm/c u option 85 ppm/c t option 70 ppm/c v rh , v rl dcp terminal voltage v rh or v rl to gnd 0v cc v r w wiper resistance rh - floating, v rl = 0v, force i w current to the wiper, i w = (v cc - v rl )/r total, v cc = 2.7v to 5.5v 70 200 ? v cc = 1.7v 580 ? c h /c l /c w terminal capacitance see ?dcp macro model? on page 8. 32 pf i lkgdcp leakage on dcp pins voltage at pin from gnd to v cc -0.4 <0.1 0.4 a noise resistor noise density wiper at middle point, w option 16 nv/ hz wiper at middle point, u option 49 nv/ hz wiper at middle point, t option 61 nv/ hz feed thru digital feedthrough from bus to wiper wiper at middle point -65 db psrr power supply reject ratio wiper output change if v cc change 10%; wiper at middle point -75 db
isl23415 5 fn7780.1 august 16, 2011 voltage divider mode (0v @ rl; v cc @ rh; measured at rw, unloaded) inl (note 13) integral non-linearity, guaranteed monotonic w option -1.0 0.5 +1.0 lsb (note 9) u, t option -0.5 0.15 +0.5 lsb (note 9) dnl (note 12) differential non-linearity, guaranteed monotonic w option -1 0.4 +1 lsb (note 9) u, t option -0.4 0.1 +0.4 lsb (note 9) fserror (note 11) full-scale error w option -3.5 -2 0 lsb (note 9) u, t option -2 -0.5 0 lsb (note 9) zserror (note 10) zero-scale error w option 0 2 3.5 lsb (note 9) u, t option 0 0.4 2 lsb (note 9) tc v (note 14) ratiometric temperature coefficient w option, wiper register set to 80 hex 8 ppm/c u option, wiper register set to 80 hex 4 ppm/c t option, wiper register set to 80 hex 2.3 ppm/c large signal wiper settling time from code 0 to ff hex 300 ns f cutoff -3db cutoff frequency wiper at middle point w option 1200 khz wiper at middle point u option 250 khz wiper at middle point t option 120 khz rheostat mode (measurements between rw and rl pins with rh not connected, or between rw and rh with rl not connected) rinl (note 18) integral non-linearity, guaranteed monotonic w option; v cc = 2.7v to 5.5v -2.0 1 +2.0 mi (note 15) w option; v cc = 1.7v 10.5 mi (note 15) u, t option; v cc = 2.7v to 5.5v -1.0 0.3 +1.0 mi (note 15) u, t option; v cc = 1.7v 2.1 mi (note 15) rdnl (note 17) differential non-linearity, guaranteed monotonic w option; v cc = 2.7v to 5.5v -1 0.4 +1 mi (note 15) w option; v cc = 1.7v 0.6 mi (note 15) u, t option; v cc = 2.7v to 5.5v -0.5 0.15 +0.5 mi (note 15) u, t option; v cc = 1.7v 0.35 mi (note 15) analog specifications v cc = 2.7v to 5.5v, v logic = 1.2v to 5.5v over recommended operating conditions unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +125c. (continued) symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units
isl23415 6 fn7780.1 august 16, 2011 r offset (note 16) offset, wiper at 0 position w option; v cc = 2.7v to 5.5v 0 3 5.5 mi (note 15) w option; v cc = 1.7v 6.3 mi (note 15) u, t option; v cc = 2.7v to 5.5v 0 0.5 2 mi (note 15) u, t option; v cc = 1.7v 1.1 mi (note 15) tcr (note 19) resistance temperature coefficient w option; wiper register set between 32 hex and ff hex 220 ppm/c u option; wiper register set between 32 hex and ff hex 100 ppm/c t option; wiper register set between 32 hex and ff hex 75 ppm/c analog specifications v cc = 2.7v to 5.5v, v logic = 1.2v to 5.5v over recommended operating conditions unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +125c. (continued) symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units operating specifications v cc = 2.7v to 5.5v, v logic = 1.2v to 5.5v over recommended operating conditions unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +125c. symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units i logic v logic supply current (write/read) v logic = 5.5v, v cc = 5.5v, f sck = 5mhz (for spi active read and write) 1.5 ma v logic = 1.2v, v cc = 1.7v, f sck = 1mhz (for spi active read and write) 30 a i cc v cc supply current (write/read) v logic = 5.5v, v cc = 5.5v 100 a v logic = 1.2v, v cc = 1.7v 10 a i logic sb v logic standby current v logic = 5.5v, v cc = 5.5v, spi interface in standby 1.3 a v logic = 1.2v, v cc = 1.7v, spi interface in standby 0.4 a i cc sb v cc standby current v logic = 5.5v, v cc = 5.5v, spi interface in standby 1.5 a v logic = 1.2v, v cc = 1.7v, spi interface in standby 1 a i logic shdn v logic shutdown current v logic = 5.5v, v cc = 5.5v, spi interface in standby 1.3 a v logic = 1.2v, v cc = 1.7v, spi interface in standby 0.4 a i cc shdn v cc shutdown current v logic = v cc = 5.5v, spi interface in standby 1.5 a v logic = 1.2v, v cc = 1.7v, spi interface in standby 1 a i lkgdig leakage current, at pins cs , sdo, sdi, sck voltage at pin from gnd to v logic -0.4 <0.1 0.4 a
isl23415 7 fn7780.1 august 16, 2011 t dcp wiper response time w option; cs rising edge to wiper new position, from 10% to 90% of final value. 0.4 s u option; cs rising edge to wiper new position, from 10% to 90% of final value. 1.5 s t option; cs rising edge to wiper new position, from 10% to 90% of final value. 3.5 s tshdnrec dcp recall time from shutdown mode cs rising edge to wiper recalled position and rh connection 1.5 s v cc , v logic ramp v cc , v logic ramp rate ramp monotonic at any level 0.01 50 v/ms operating specifications v cc = 2.7v to 5.5v, v logic = 1.2v to 5.5v over recommended operating conditions unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +125c. (continued) symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units serial interface specification for sck, sdi, sdo, cs unless otherwise noted. symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units v il input low voltage -0.3 0.3 x v logic v v ih input high voltage 0.7 x v logic v logic + 0.3 v hysteresis sdi and sck in put buffer hysteresis v logic > 2v 0.05 x v logic v v logic < 2v 0.1 x v logic v ol sdo output buffer low voltage i ol = 3ma, v logic > 2v 0 0.4 v i ol = 1.5ma, v logic < 2v 0.2 x v logic v r pu (note 19) sdo pull-up resistor off-chip maximum is determined by t ro and t fo with maximum bus load cb = 30pf, f sck =5mhz 1.5 k c pin sck, sdo, sdi, cs pin capacitance 10 pf f sck sck frequency v logic = 1.7v to 5.5v 5 mhz v logic = 1.2v to 1.6v 1 mhz t cyc spi clock cycle time v logic 1.7v 200 ns t wh spi clock high time v logic 1.7v 100 ns t wl spi clock low time v logic 1.7v 100 ns t lead lead time v logic 1.7v 250 ns t lag lag time v logic 1.7v 250 ns t su sdi, sck and cs input setup time v logic 1.7v 50 ns t h sdi, sck and cs input hold time v logic 1.7v 50 ns t ri sdi, sck and cs input rise time v logic 1.7v 10 ns t fi sdi, sck and cs input fall time v logic 1.7v 10 20 ns t dis sdo output disable time v logic 1.7v 0 100 ns t so sdo output setup time v logic 1.7v 50 ns t v sdo output valid time v logic 1.7v 150 ns t ho sdo output hold time v logic 1.7v 0 ns t ro sdo output rise time r pu = 1.5k, cbus = 30pf 60 ns t fo sdo output fall time r pu = 1.5k, cbus = 30pf 60 ns
isl23415 8 fn7780.1 august 16, 2011 dcp macro model t cs cs deselect time 2 s notes: 8. typical values are for t a = +25c and 3.3v supply voltages. 9. lsb = [v(rw) 255 ? v(rw) 0 ] / 255. v(rw) 255 and v(rw) 0 are v(rw) for the dcp register set to ff hex and 00 hex respectively. lsb is the incremental voltage when changing from one tap to an adjacent tap. 10. zs error = v(rw) 0 / lsb. 11. fs error = [v(rw) 255 ? v cc ] / lsb. 12. dnl = [v(rw) i ? v(rw) i-1 ] / lsb-1, for i = 1 to 255. i is the dcp register setting. 13. inl = [v(rw) i ? i ? lsb ? v(rw) 0 ]/lsb for i = 1 to 255 14. for i = 16 to 255 decimal, t = -40c to +125c. max( ) is the maximum value of the wiper voltage and min( ) is the minimum value of the wiper voltage over the temperature range. 15. mi = | rw 255 ? rw 0 | / 255. mi is a minimum increment. rw 255 and rw 0 are the measured resistances for the dcp register set to ff hex and 00 hex respectively. 16. roffset = rw 0 / mi, when measuring between rw and rl. roffset = rw 255 / mi, when measuring between rw and rh. 17. rdnl = (rw i ? rw i-1 ) / mi -1, for i = 16 to 255. 18. rinl = [rw i ? (mi ? i) ? rw 0 ] / mi, for i = 16 to 255. 19. for i = 16 to 255, t = -40c to +125c. max( ) is th e maximum value of the resistance and min( ) is the minimum value of the resistance over the temperature range. 20. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. serial interface specification for sck, sdi, sdo, cs unless otherwise noted. (continued) symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units t c v max v rw () i () min v rw () i () ? vrwi+25c () () ----------------------------------------------------------------------------- - 10 6 +165c --------------------- = t c r max ri () min ri () ? [] ri +25c () ------------------------------------------------------ - 10 6 +165c --------------------- = 32pf rh r total c h 32pf c w c l 32pf rw rl timing diagrams input timing ... cs sck sdi sdo msb lsb t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh
isl23415 9 fn7780.1 august 16, 2011 output timing xdcp? timing (for all load instructions) timing diagrams (continued) ... cs sck sdo sdi addr msb lsb t dis t ho t v ... t so ... cs sck sdi msb lsb v w t dcp ... sdo *when cs is high sdo at z or hi-z state typical performance curves figure 3. 10k dnl vs tap position, v cc = 5v figure 4. 50k dnl vs tap position, v cc = 5v -0.4 -0.2 0 0.2 0.4 0 50 100 150 200 250 d n l ( l s b ) tap position (decimal) -0.30 -0.15 0 0.15 0.30 0 50 100 150 200 250 d n l ( l s b ) tap position (decimal)
isl23415 10 fn7780.1 august 16, 2011 figure 5. 10k inl vs tap position, v cc = 5v figure 6. 50k inl vs tap position, v cc = 5v figure 7. 10k rdnl vs tap position, v cc = 5v figure 8. 50k rdnl vs tap position, v cc = 5v figure 9. 10k rinl vs tap position, v cc = 5v figure 10. 50k rinl vs tap position, v cc = 5v typical performance curves (continued) -0.4 -0.2 0 0.2 0.4 0 50 100 150 200 250 i n l ( l s b ) tap position (decimal) -0.30 -0.15 0 0.15 0.30 0 50 100 150 200 250 i n l ( l s b ) tap position (decimal) -0.4 -0.2 0 0.2 0.4 0 50 100 150 200 250 r d n l ( m i ) tap position (decimal) -0.30 -0.15 0 0.15 0.30 0 50 100 150 200 250 r d n l ( m i ) tap position (decimal) -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0 50 100 150 200 250 r i n l ( m i ) tap position (decimal) -0.30 -0.15 0 0.15 0.30 0 50 100 150 200 250 r i n l ( m i ) tap position (decimal)
isl23415 11 fn7780.1 august 16, 2011 figure 11. 10k wiper resistance vs tap position, v cc = 5v figure 12. 50k wiper resistance vs tap position, v cc = 5v figure 13. 10k tcv vs tap position figure 14. 50k tcv vs tap position figure 15. 10k tcr vs tap position figure 16. 50k tcr vs tap position typical performance curves (continued) 0 10 20 30 40 50 60 70 0 50 100 150 200 250 w i p e r r e s i s t a n c e ( ) tap position (decimal) +125c -40c +25c 0 10 20 30 40 50 60 0 50 100 150 200 250 tap position (decimal) w i p e r r e s i s t a n c e ( ) +125c -40c +25c 0 50 100 150 200 250 300 15 65 115 165 215 t c v ( p p m / c ) tap position (decimal) 0 10 20 30 40 50 60 70 15 65 115 165 215 t c v ( p p m / c ) tap position (decimal) 0 100 200 300 400 500 600 15 65 115 165 215 t c r ( p p m / c ) tap position (decimal) 0 50 100 150 200 15 65 115 165 215 t c r ( p p m / c ) tap position (decimal)
isl23415 12 fn7780.1 august 16, 2011 figure 17. 100k tcv vs tap position figure 18. 100k tcr vs tap position figure 19. wiper digital feedthroug h figure 20. wiper transition glitch figure 21. wiper large signal settling time figure 22. power-on start-up in voltage divider mode typical performance curves (continued) 0 5 10 15 20 25 30 35 15 65 115 165 215 t c v ( p p m / c ) tap position (decimal) 0 30 60 90 120 15 65 115 165 215 t c r ( p p m / c ) tap position (decimal) 10mv/div 1s/div rw pin sck clock 20mv/div 5s/div 1v/div 1s/div cs rising edge vrw 1v/div 0.1s/div
isl23415 13 fn7780.1 august 16, 2011 functional pin description potentiometers pins rh and rl the high (rh) and low (rl) te rminals of the isl23415 are equivalent to the fixed terminals of a mechanical potentiometer. the rh and rl are referenced to th e relative position of the wiper and not the voltage potential on the terminals. with the wr register set to 255 decimal, the wiper will be closest to rh, and with the wr register set to 0, the wiper is closest to rl. rw the rw is the wiper terminal, and it is equivalent to the moveable terminal of a mechanic al potentiometer. the position of the wiper within the array is determined by the wr register. power pins v cc power terminal for the potentiometer section analog power source. can be any value needed to support voltage range of dcp pins, from 1.7v to 5.5v, independent of the v logic voltage. bus interface pins serial clock (scl) this input is the serial clock of the spi serial interface. serial data input (sdi) the sdi is a serial data input pin for spi interface. it receives operation code, wiper address and data from the spi remote host device. the data bits are shif ted in at the rising edge of the serial clock sck, while the cs input is low. serial data output (sdo) the sdo is a serial data output pi n. during a read cycle, the data bits are shifted out on the falling edge of the serial clock sck and will be available to the master on the following rising edge of sck. the output type is configured th rough acr[1] bit for push-pull or open drain operation. de fault setting for this pin is push-pull. an external pull-up resistor is required for open drain output operation. when cs is high, the sdo pin is in tri-state (z) or high-tri-state (hi-z) depends on the selected configuration. chip select (cs ) cs low enables the isl23415, placing it in the active power mode. a high to low transition on cs is required prior to the start of any operation after power-up. when cs is high, the isl23415 is deselected and the sd o pin is at high impedance, and the device will be in the standby state. v logic digital power source for the logic control section. it supplies an internal level translator for 1.2v to 5.5v serial bus operation. use the same supply as the i 2 c logic source. principles of operation the isl23415 is an integrated circuit incorporating one dcp with its associated registers and an spi serial interface providing direct communication between a host and the potentiometer. the resistor array is comprised of individual resistors connected in series. at either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. the electronic switches on the device operate in a ?make before break? mode when the wiper changes tap positions. voltage at any dcp pins, rh, rl or rw, should not exceed v cc level at any conditions during power-up and normal operation. the v logic pin needs to be connected to the spi bus supply which allows reliable communic ation with the wide range of microcontrollers and independent of the v cc level. this is extremely important in system s where the digital supply has lower levels than the analog supply. figure 23. 10k -3db cut off frequency figure 24. standby current vs temperature typical performance curves (continued) r total = 10k -3db frequency = 1.4mhz at middle tap ch1: 0.5v/div, 0.2s/div rh pin ch2: 0.2v/div, 0.2s/div rw pin 0 0.2 0.4 0.6 0.8 1.0 1.2 -40 -15 10 35 60 85 110 s t a n d b y c u r r e n t i c c ( a ) temperature (c) v cc = 5.5v, v logic = 5.5v v cc = 1.7v, v logic = 1.2v
isl23415 14 fn7780.1 august 16, 2011 dcp description each dcp is implemented with a combination of resistor elements and cmos switches. the physical ends of dcp are equivalent to the fixed terminal s of a mechanical potentiometer (rh and rl pins). the rw pin of the dcp is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. the po sition of the wiper terminal within the dcp is controlled by the 8-bit volatile wiper register (wr). when the wr of a dcp contains all zeroes (wr[7:0] = 00h), its wiper terminal (rw) is closest to its ?low? terminal (rl). when the wr register of a dcp contains all ones (wr[7:0] = ffh), its wiper terminal (rw) is closest to its ?high? terminal (rh). as the value of the wr increases from all zeroes (0) to all ones (255 decimal), the wiper moves mono tonically from the position closest to rl to the position closest to rh. at the same time, the resistance between rw and rl increases monotonically, while the resistance between rh an d rw decreases monotonically. while the isl23415 is being powere d up, the wr is reset to 80h (128 decimal), which locates rw roughly at the center between rl and rh. the wr can be read or written to directly using the spi serial interface as described in the following sections. memory description the isl23415 contains two volati le 8-bit registers: the wiper register (wr) and the access control register (acr). memory map of isl23415 is in table 1. the wiper register wr at address 0 contains current wiper position of the dcp. the access control register (acr) at address 10h co ntains information and control bits described in table 2. the sdo bit (acr[1]) configures type of sdo output pin. the default value of sdo bit is 0 for push-pull output. the sdo pin can be configured as open drain output for some applications. in this case, an external pull-up re sistor is required, reference the ?serial interface specification? on page 7. shutdown function the shdn bit (acr[6]) disables or enables shutdown mode for all dcp channels simultaneously. when this bit is 0, i.e., each dcp is forced to end-to-end open circuit and each rw shorted to rl through a 2k ? serial resistor, as shown in figure 25. default value of the shdn bit is 1. when the device enters shutdown, all current dcp wr settings are maintained. when the device exits shutdown, the wipers will return to the previous wr settings after a short settling time (see figure 26). spi serial interface the isl23415 supports an spi serial protocol, mode 0. the device is accessed via the sdi input and sdo output with data clocked in on the rising edge of sck, and clocked out on the falling edge of sck. cs must be low during communication with the isl23415. the sck and cs lines are controlled by the host or master. the isl23415 operates only as a slave device. all communication over the spi interface is conducted by sending the msb of each byte of data first. protocol conventions the spi protocol contains instructio n byte followed by one or more data bytes. a valid instruction byte contains instruction as the three msbs, with the following five regi ster address bits (see table 3). the next byte sent to the isl23415 is the data byte. table 4 contains a valid instruction set for isl23415. if the [r4:r0] bits are zero or one, then the read or write is to the wri register. if the [r4:r0] are 10000, then the operation is to the acr. table 1. memory map address (hex) volatile default setting (hex) 10 acr 40 0wr 80 table 2. access control register (acr) bit # 76543210 name 0shdn 00 0 0sdo0 figure 25. dcp connection in shutdown mode figure 26. shutdown mode wiper response table 3. instruction byte format bit #76543210 i2 i1 i0 r4 r3 r2 r1 r0 2k ? rw rl rh power-up user programmed mid scale = 80h shdn activated shdn released after shdn wiper voltage, v rw (v) shdn mode time (s) wiper restore to the original position 0
isl23415 15 fn7780.1 august 16, 2011 write operation a write operation to the isl23415 is a two or more bytes operation. it requires first, the cs transition from high-to-low. then the host sends a valid instruction byte, followed by one or more data bytes to the sdi pin. the host terminates the write operation by pulling the cs pin from low-to-high. instruction is executed on the rising edge of cs (see figure 27). read operation a read operation to the isl23415 is a four byte operation. it requires first, the cs transition from high-to-low. then the host sends a valid instruction byte, followed by a ?dummy? data byte, nop instruction byte and another ?dummy? data byte to sdi pin. the spi host receives the instru ction byte (instruction code + register address) and requested data byte from sdo pin on the rising edge of sck during third and fourth bytes, respectively. the host terminates the read by pulling the cs pin from low-to-high (see figure 28). table 4. instruction set instruction set operation i2 i1 i0 r4 r3 r2 r1 r0 000xxxxxnop 001xxxxxacr read 011xxxxxacr wrte 1 0 0 r4r3r2r1r0wri or acr read 1 1 0 r4r3r2r1r0wri or acr wrte where x means ?do not care?. figure 27. two byte write sequence cs sck sdi sdo wr instruction data byte 1 3 4 5 7 8 9 10111213141516 26 addr figure 28. four by te read sequence cs sck sdi sdo rd addr nop rd addr read data 1 8 16 24 32
isl23415 16 fn7780.1 august 16, 2011 applications information communicating with isl23415 communication with isl23415 proceeds using spi interface through the acr (address 10000b) and wr (addresses 00000b) registers. the wiper of the potentiometer is controlled by the wr register. writes and reads can be made directly to these register to control and monitor the wiper position. daisy chain configuration when application needs more than one isl23415, it can communicate with all of them without additional cs lines by daisy chaining the dcps as shown on figure 29. in daisy chain configuration, the sdo pin of the previous chip is connected to the sdi pin of the following chip, and each cs and sck pins are connected to the corresponding mi crocontroller pins in parallel, like regular spi interface implementation. the daisy chain configuration can also be used for simultaneous setting of multiple dcps. note, the number of daisy chained dcps is limited only by the drivin g capabilities of sck and cs pins of microcontroller; for larger number of spi devices buffering of sck and cs lines is required. daisy chain write operation the write operation starts by high-to-low transition on cs line, followed by n number of two bytes write instructions on sdi line with reversed chain access sequen ce: the instruction byte + data byte for the last dcp in chain is going first, as shown in figure 30, where n is a number of dcps in chain. the serial data is going through dcps from dcp0 to dcp(n-1) as follow: dcp0 --> dcp1 --> dcp2 --> ... --> dcp(n-1). the write instruction is executed on the rising edge of cs for all n dcps simultaneously. daisy chain read operation the read operation consists of two parts: first, send the read instructions (n two bytes operatio n) with valid ad dress; second, read the requested data while sending nop instructions (n two bytes operation) as shown in figures 31 and 32. the first part starts by high-to-low transition on cs line, followed by n two bytes read instruction on sdi line with reversed chain access sequence: the instru ction byte + dummy data byte for the last dcp in chain is going first, followed by low-to-high transition on cs line. the read instructions are executed during second part of read sequence. it also starts by high-to-low transition on cs line, followed by n number of two bytes nop instructions on sdi line and low-to-high transition of cs . the data is read on every even byte during second part of read sequence while every odd byte contains code 111b followed by address from which the data is being read. wiper transition when stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance ?make? to a much higher impedance ?break within a short pe riod of time (<1s). there are several code transitions such as 0fh to 10h, 1fh to 20h,..., efh to ffh, which have higher transient glitch. note, that all switching transients will settle well within the settling time as stated in the datasheet. a small capacitor can be added externally to reduce the amplitude of these voltage transients, but that will also reduce the useful bandwidth of the circuit, thus may not be a good solution for some applications. it may be a good idea, in that case, to use fast amplifie rs in a signal chain for fast recovery. v logic requirements it is recommended to keep v logic powered all the time during normal operation. in a case where turning v logic off is necessary, it is recomme nded to ground the v logic pin of the isl23415. grounding the v logic pin or both v logic and v cc does not affect other devices on the same bus. it is good practice to put a 1f capacitor in parallel with 0.1f decoupling capacitor close to the v logic pin. v cc requirements and placement it is recommended to put a 1f capacitor in parallel with 0.1f decoupling capacitor close to the v cc pin. cs sck mosi miso cs sck sdi sdo cs sck sdi sdo cs sck sdi sdo cs sck sdi sdo c dcp0 dcp1 dcp2 dcp(n-1) figure 29. daisy chain configuration n dcp in a chain
isl23415 17 fn7780.1 august 16, 2011 cs sck sdi sdo 0 wr d c p2 wr d c p1 wr d c p0 wr d c p1 sdo 1 wr d c p2 sdo 2 wr d c p2 figure 30. daisy chain write sequence of n = 3 dcp 16 clkls 16 clks 16 clks figure 31. two byte read instruction cs sck sdi sdo instruction addr data in data out 1 2 10 11 12 13 14 15 16 345 67 8 9 cs sck sdi sdo rd dcp1 rd dcp0 nop nop nop dcp2 out dcp1 out dcp0 out rd dcp2 16 clks 16 clks 16 clks 16 clks 16 clks 16 clks figure 32. daisy chain read sequence of n = 3 dcp
isl23415 18 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7780.1 august 16, 2011 for additional products, see www.intersil.com/product_tree revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. products intersil corporation is a leader in the desi gn and manufacture of high-performance an alog semiconductors. the company's product s address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. in tersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl23415 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php date revision change 12/15/10 fn7780.0 initial release. 7/28/11 fn7780.1 added ?shutdown function? section and revised ?v logic standby current?and ?v cc shutdown current? limits on page 6. on page 7, split ?wiper response time? up into 3 separate conditions for each option (w, u, t).
isl23415 19 fn7780.1 august 16, 2011 mini small outline pl astic packages (msop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m - 1994. 3. dimension ?d? does not include mold flash, protrusions or gate burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not includ e interlead flash or protrusions and are measured at datum plane. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. formed leads shall be planar wi th respect to one another within 0.10mm (.004) at seating plane. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums and to be determined at datum plane . 11. controlling dimension: millimeter. converted inch dimen- sions are for reference only l 0.25 (0.010) l1 r1 r 4x 4x gauge plane seating plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a b c seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side view b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a - h - -a - - b - - h - m10.118 (jedec mo-187ba) 10 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.007 0.011 0.18 0.27 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.020 bsc 0.50 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n10 107 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 5 o 15 o 5 o 15 o - 0 o 6 o 0 o 6 o - rev. 0 12/02
isl23415 20 fn7780.1 august 16, 2011 package outline drawing l10.2.1x1.6a 10 lead ultra thin quad flat no-lead plastic package rev 5, 3/10 bottom view detail "x" side view typical recommended land pattern top view 1 2x 0.10 1.60 2.10 b a index area pin 1 1 (6x 0.50 ) (10 x 0.20) (0.10 min.) (0.05 min) 8. (10x 0.60) package (2.00) (0.80) (1.30) (2.50) 0.08 seating plane 0.10 c c c see detail "x" max. 0.55 0 . 125 ref 0-0.05 c 6 9 1 5 6x 0.50 c c 10 x 0.20 4 0.10 m ma b 0.80 pin #1 id 4 10 0.10 min. 0.05 min. 4x 0.20 min. 8. 10x 0.40 outline lead width dimension applies to the metallized terminal and is measured the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. dimensioning and tolerancing conform to asme y14.5m-1994. unless otherwise specified, tolerance : decimal 0.05 1. all dimensions are in millimeters. angles are in degrees. dimensions in ( ) for reference only. between 0.15mm and 0.30mm from the terminal tip. maximum package warpage is 0.05mm. 4. 5. 2. 3. notes: maximum allowable burrs is 0.076mm in all directions. 6. same as jedec mo-255uabd except: 7. no lead-pull-back, min. package thickness = 0.45 not 0.50mm lead length dim. = 0.45mm max. not 0.42mm. 8.

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